1. Field of the Invention
This invention relates to a Random Access Memory (RAM) device and more particularly, a method for fabricating a Dynamic Random Access Memory (DRAM) device having a stacked storage capacitor with increased capacitance.
2. Description of the Prior Art
Advances in semiconductor technologies have dramatically increased the circuit density on a chip. For example, advances in photolithographic techniques, such as phase-shifting masks, self-aligning process steps and directional plasma etching have further reduced the device size and increased circuit density. This has lead to Ultra Large Scale Integration (ULSI) on semiconductor substrates with minimum device dimensions less than a micrometer and more than a million transistors formed on a chip cut (diced) from the substrate. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One type of circuit elements experiencing electrical limitations is the array of storage cells formed on a Dynamic Random Access Memory (DRAM) chip. These DRAM devices having arrays of storage cells, each cell consisting of a single field effect transistor (FET) and a single capacitor are used extensively in the electronic industry, and particularly in the computer industry, for storing data. The individual DRAM cell stores a bit of data on a capacitor as electrical charge.
With increasing circuit density, the array of cells on the DRAM chip increase in number and the individual capacitors decreases in size. This makes it more difficult to maintain sufficient charge on the capacitor to achieve acceptable signal-to-noise level. Also, because of leakage currents, these volatile storage cells require more frequent refresh cycles to maintain their charge level.
The storage capacitors are either formed in the substrate, usually referred to as trench capacitor, or are formed on the substrate over the field effect transistor and are usually referred to as stacked capacitors. The latter approach has received considerable attention in recent years because of the flexibility in fabricating the capacitor during processing. However, since each stacked capacitor, in the array of cells, are confined within the cell area, it is difficult to maintain sufficient capacitance as the cell density increases and the cell size decreases. As conventional methods of high resolution photolithography and anisotropic etching reach their limits, it becomes necessary to explore other methods for increasing the capacitance.
One method of increasing the capacitance is to roughen the surface of the bottom electrode of the capacitor to effectively increase the surface area without increasing its overall size. See, for example, H. C. Tuan et.al. U.S. Pat. No. 5,266,514. Another approach is to use an interelectrode insulator having a high dielectric constant. See for example, "A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al, IEEE International Electronic Device Meeting Proceedings, Dec 1993 page 631-634.
Still another approach is to build three dimensional capacitor structure extending vertically upward over and within the cell area. For example, A. Chiba, U.S. Pat. No. 5,102,820, uses a patterned multilayer of polysilicon and silicon oxide with polysilicon sidewall to make a vertical capacitor with a cavity formed therein to increase the surface area of the capacitor. Another approach is described by H. Ogawa et al, U.S. Pat. No. 5,164,337 having a similar structure as U.S. Pat. No. 5,102,820, but made by forming a multi-layer insulating template and then depositing a conformal polysilicon layer thereon to form a capacitor with increased area. And yet another approach is described by C. Kudoh et al, U.S. Pat. No. 5,223,729 in which a multilayer of polysilicon and silicon oxide are patterned and the oxide is removed forming a fin-shaped capacitor.
However, many of these methods require etching a contact opening having vertical sidewalls through a multilayer of polysilicon and oxide which is difficult to achieve. Other methods rely on forming sidewall polysilicon structures to form a continuous capacitor electrode, which is also difficult to manufacture. In general, much of the prior art mentioned above require significantly more processing steps which increase manufacturing cost and reduce process yields.
A relatively simple prior art DRAM process for increasing the cell capacitance is now described with reference to the schematic cross sections shown in FIGS. 1 through 4, so as to better understand the nature of the problem solved. Referring to FIG. 1, a substrate 10 is provided, such as P.sup.- doped single crystal silicon, having device areas surrounded and electrically isolated by a Field OXide (FOX) 12. Only one cell area of the array of cells fabricated simultaneously on the substrate is depicted in the Figs. A gate oxide layer 14, for the FET, is formed on the device area and then word lines, patterned from a N doped conductive polysilicon layer 16 are formed having portions over the gate oxide 14 serving as FET gate electrodes 16. Usually an insulating layer 18 is formed over the gate electrode 16 at the same time the electrode is formed. For very short channel FETs, it is common practice in the semiconductor industry, to form lightly doped drain (LDD) FETs to improve the electrical characteristics of the FET. This is accomplished by implanting an N-type dopant at low dose in the source/drain areas 20 adjacent to the gate electrode 16 and then protecting the LDD region by forming a insulating sidewall spacer 22 using an anisotropically etch back of an insulating layer, such as SiO.sub.2. A high dose N-type implant is then carried out to form the source/drain regions 24 and complete the LDD FET.
The DRAM stacked capacitor of this prior art having a fin-shaped extension to increase capacitance is then formed by first depositing a multi-layer insulating film composed of a silicon oxide layer 30, a silicon nitride layer 32 and another silicon oxide layer 34. Also shown in FIG. 1. Contact openings 40 (only one shown in FIG. 2) are then etched to one of the two source/drain regions 24 of each FET. The bottom electrode of the stacked capacitor is formed by depositing a polysilicon layer 42, that is also doped N.sup.+ type, and patterning layer 42 to form the fin-shaped bottom electrode 42 having increased surface area. The silicon oxide layer 34 is now isotropically etched in, for example, a hydrofluoric acid solution removing completely layer 34 and leaving a free standing fin-shaped bottom electrode 42, as shown in FIG. 3. A thin capacitor dielectric 44 is formed on the bottom electrode 42 and a second N+ doped polysilicon layer 50 is deposited to form the top electrode of the capacitor and complete the stacked capacitor storage cell. However, as the cell size decreases with increased packing density, the fin-shaped electrode 42 must also decrease in surface area.
Therefore, there is still a strong need to develop a stacked capacitor process that is as simple as possible, avoids the difficult processing problems, and does not substantially increase the number of process steps while maintaining as large a surface area as possible.